MAX1195ECM+TD【PDF 19/22 页】IC ADC 8BIT 40MSPS DL 48-TQFP

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Sheet目录2008

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MAX1195

Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________

Note 1: Guaranteed by design. Not subject to production testing.

Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.

Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two

applied input signals with the same magnitude (peak-to-peak) at fIN1 and fIN2.

Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor.

Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1F (min) and 2.2F (typ) capacitor.

Note 6: Typical analog output current at fINA&B = 20MHz. For digital output currents vs. analog input frequency,

see Typical Operating Characteristics.

Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock

level to 50% of the data output level.

Note 8: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.

Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.

Note 9: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-

mental of the calculated FFT.

Note 10: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental

of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.

Note 11: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid

Time

tDO

CL = 20pF (Notes 1, 7)

OE Fall to Output Enable Time

tENABLE

5ns

OE Rise to Output Disable Time

tDISABLE

5ns

CLK Pulse Width High

tCH

Clock period: 25ns (Note 7)

12.5

±1.5

CLK Pulse Width Low

tCL

Clock period: 25ns (Note 7)

12.5

±1.5

Wake up from sleep mode

Wake-Up Time

tWAKE

Wake up from shutdown mode (Note 11)

CHANNEL-TO-CHANNEL MATCHING

Crosstalk

fINA or B = 20MHz at -1dB FS (Note 8)

-72

Gain Matching

fINA or B = 20MHz at -1dB FS (Note 9)

0.05

Phase Matching

fINA or B = 20MHz at -1dB FS (Note 10)

±0.05

Degrees

ELECTRICAL CHARACTERISTICS (continued)

(VDD = OVDD = 3V, 0.1F and 2.2F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k

resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 40MHz, TA = TMIN to TMAX, unless

otherwise noted.

≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at

TA = +25°C.)

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